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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 2001 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com cs4360 24-bit, 192 khz 6 channel d/a converter features l 24-bit conversion l 102 db dynamic range l -90 db thd+n l +3 v to +5 v power supply l digital volume control with soft ramp C 119 db attenuation C 1 db step size C zero crossing click-free transitions l low power consumption C 105 mw with 3 v supply l atapi mixing l low clock jitter sensitivity l popguard technology ? for control of clicks and pops description the cs4360 is a complete 6-channel digital-to-analog system including digital interpolation, fourth-order delta- sigma digital-to-analog conversion, digital de-emphasis, volume control, channel mixing and analog filtering. the advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and tempera- ture and a high tolerance to clock jitter. the cs4360 accepts data at audio sample rates from 4 khz to 200 khz, consumes very little power and oper- ates over a wide power supply range. these features are ideal for cost-sensitive, multi-channel audio systems in- cluding dvd players, a/v receivers, set-top boxes, digital tvs and vcrs, mini-component systems, and mixing consoles. ordering information cs4360-ks -10 to 70 c 28-pin soic CS4360-BS -40 to 85 c 28-pin soic cs4360-kz -10 to 70 c 28-pin tssop cs4360-bz -40 to 85 c 28-pin tssop cdb4360 evaluation board i control port external mute control rst volume control interpolation filter analog filter ao ut a1 ds dac mixer volume control ds dac analog filter ao utb1 interpolation filter volume control interpolation filter analog filter ao ut a2 ds dac mixer volume control ds dac analog filter ao utb2 interpolation filter volume control interpolation filter analog filter ao ut a3 ds dac mixer volume control ds dac analog filter ao ut b3 interpolation filter mclk serial port lrck sclk sd i n1 sd i n2 sd i n3 dif1/scl/cclk dif0/sda/cdin m1/ad0/cs vlc 2 vq filt+ va gnd vd vls mutec1 mutec2 mutec3 m2 gnd feb 01 ds517pp1
cs4360 2 ds517pp1 table of contents 1. characteristics and specifications ......................................................................... 5 analog characteristics ................................................................................................ 5 power and thermal characteristics....................................................................... 7 digital characteristics ................................................................................................. 7 absolute maximum ratings ........................................................................................... 7 recommended operating conditions ....................................................................... 8 switching characteristics .......................................................................................... 9 switching characteristics- control port- two-wire format .................... 10 switching characteristics - control port - spi format ............................... 11 2. typical connection diagram....................................................................................... 12 3. register quick reference ........................................................................................... 13 4. register descriptions ................................................................................................... 14 4.1 mode control 1 (address 01h) ......................................................................................... 14 4.1.1 auto-mute (amute) ...................................................................................................... 14 4.1.2 digital interface format (dif) ........................................................................................ 14 4.1.3 de-emphasis control (dem) ......................................................................................... 15 4.1.4 functional mode (fm).................................................................................................... 1 5 4.2 invert signal (address 02h)............................................................................................. 1 5 4.2.1 invert signal polarity (inv_xx) ....................................................................................... 15 4.3 mixing control pair 1 (channels a1 & b1) (address 03h) mixing control pair 2 (channels a2 & b2) (address 04h) mixing control pair 3 (channels a3 & b3) (address 05h)............................................. 15 4.3.1 atapi channel mixing and muting (atapi) .................................................................. 16 4.4 volume control (addresses 06h - 0bh)............................................................................ 16 4.4.1 mute (mute) ............................................................................................................. ... 16 4.4.2 volume control (xx_vol) ............................................................................................. 17 4.5 mode control 2 (address 0dh)........................................................................................ 17 4.5.1 soft ramp and zero cross control (szc) ..................................................................... 17 4.5.2 control port enable (cpen) .......................................................................................... 18 4.5.3 power down (pdn)........................................................................................................ 1 8 4.5.4 popguard? transient control (popg) ......................................................................... 18 4.5.5 freeze controls (freeze)............................................................................................ 18 4.5.6 master clock divide enable (mclkdiv) ....................................................................... 18 4.5.7 single volume control (snglvol)............................................................................... 19 4.6 revision register (read only) (address 0dh)............................................................... 19 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. cirrus logic, inc. has made best effort s to ensure that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provi d ed as is without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information to verify, before pla cing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of o rder acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. no responsibility is assumed by cirrus logic, inc. f or the use of this information, including use of this information as the basis for manufacture or sale of any items, nor for infringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and by furnishing this information, cirrus logic, inc. grants no license, express or implied un der any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights of cirrus logic, inc. cirrus logic, inc., copyrigh t owner of the information contained herein, gives consent for copies to be made of the information only for use within your organization with respect to cirrus log ic integrated circuits or other parts of cirrus logic, inc. the same consent is given for similar information contained on any cirrus logic website or disk. this c onsent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. the names of products of cirrus logic, inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners wh ich may be registered in some jurisdictions. a list of cirrus logic, inc. trademarks and service marks can be found at http://www.cirrus.com .
cs4360 ds517pp1 3 4.6.1 revision indicator (rev) [read only] ........................................................................... 19 5. pin description............................................................................................................ ...... 20 6. applications ............................................................................................................... ....... 23 6.1 grounding and power supply decoupling........................................................................ 23 6.2 oversampling modes........................................................................................................ 2 3 6.3 recommended power-up sequence................................................................................ 23 6.4 popguard? transient control........................................................................................... 23 7. control port interface............................................................................................... 24 7.1 enabling the control port ................................................................................................. 2 4 7.2 format selection ........................................................................................................... ... 24 7.3 two-wire format............................................................................................................ .. 24 7.3.1 writing in two-wire format ................................................................................. 24 7.3.2 reading in two-wire format ............................................................................... 25 7.4 spi format ................................................................................................................. ...... 25 7.4.1 writing in spi ....................................................................................................... 25 7.5 memory address pointer (map) ...................................................................................... 26 7.5.1 incr (auto map increment enable) .............................................................................. 26 7.5.2 map (memory address pointer) .................................................................................... 26 8. parameter definitions................................................................................................... 32 total harmonic distortion + noise (thd+n) .......................................................................... 32 dynamic range .................................................................................................................. .... 32 interchannel isolation ......................................................................................................... .... 32 interchannel gain mismatch ................................................................................................... 32 gain error ..................................................................................................................... .......... 32 gain drift ..................................................................................................................... ........... 32 9. references................................................................................................................. ........ 32 10. package dimensions ..................................................................................................... 33 list of figures figure 1. serial mode input timing ............................................................................................. .. 9 figure 2. control port timing - two-wire format ....................................................................... 10 figure 3. control port timing - spi format ................................................................................. 11 figure 4. typical connection diagram ........................................................................................ 12 figure 5. control port timing, two-wire format ........................................................................ 25 figure 6. control port timing, spi format .................................................................................. 25 figure 7. base-rate stopband rejection .................................................................................... 27 figure 8. base-rate transition band .......................................................................................... 27 figure 9. base-rate transition band (detail) ............................................................................. 27 figure 10. base-rate passband ripple ........................................................................................ 27 figure 11. high-rate stopband rejection .................................................................................... 27 figure 12. high-rate transition band ........................................................................................... 27 figure 13. high-rate transition band (detail) .............................................................................. 28 figure 14. high-rate passband ripple ......................................................................................... 28 figure 15. output test load .................................................................................................... ..... 28 figure 16. maximum loading ..................................................................................................... ... 28 figure 17. cs4360 format 0 - left justified upto 24-bit data ....................................................... 29 figure 18. cs4360 format 1 - i 2 s upto 24-bit data ...................................................................... 29 figure 19. cs4360 format 2 - right justified 16-bit data ............................................................ 29 figure 20. cs4360 format 3 - right justified 24-bit data ............................................................ 29 figure 21. cs4360 format 4 - right justified 20-bit data ............................................................ 30
cs4360 4 ds517pp1 figure 22. cs4360 format 5 - right justified 18-bit data ............................................................ 30 figure 23. de-emphasis curve ................................................................................................... .. 30 figure 24. atapi block diagram ................................................................................................. .31 list of tables table 1. digital interface formats - control port mode .................................................................... 14 table 2. atapi decode.......................................................................................................... .......... 16 table 3. example digital volume settings ....................................................................................... 17 table 4. digital interface formats - stand alone mode.................................................................... 21 table 5. mode selection........................................................................................................ ........... 21 table 6. single-speed mode common clock frequencies.............................................................. 22 table 7. double-speed mode common clock frequencies ............................................................ 22 table 8. quad-speed mode common clock frequencies............................................................... 22
cs4360 ds517pp1 5 1. characteristics and specifications analog characteristics (full-scale output sine wave, 997 hz; for single-speed mode, fs = 48 khz, sclk = 3.072 mhz, mclk = 12.288 mhz; for double-speed mode fs = 96 khz, sclk = 6.144 mhz, mclk = 12.288 mhz; for quad-speed mode fs = 192 khz, sclk = 12.288 mhz, mclk = 24.576 mhz; measure- ment bandwidth 10 hz to 20 khz, unless otherwise specified. test load r l = 10 k w, c l = 10 pf (see figure 15). va = vd = vls = vlc), notes: 1. cs4360-ks/-kz parts are tested at 25 c. 2. one-half lsb of triangular pdf dither is added to data. 3. CS4360-BS/-bz parts are tested at the extremes of the specified temperature range and min/max performance numbers are guaranteed across the specified temperature range, t a . typical numbers are taken at 25 c. analog characteristics (continued) parameter va = 5 v va = 3 v symbol min typ max min typ max unit cs4360-ks/-kz dynamic performance (note 1) specified temperature range t a -10 - 70 -10 - 70 c dynamic range (note 2) unweighted a-weighted 40 khz bandwidth a-weighted tbd tbd - 99 102 100 - - - tbd tbd - 94 97 97 - - - db db db total harmonic distortion + noise (note 2) 0 db -20 db -60 db thd+n - - - - -91 -79 -39 tbd - - - - - -91 -74 -34 tbd - - db db db interchannel isolation (1 khz) - 102 - - 102 - db CS4360-BS/-bz dynamic performance (note 3) specified temperature range t a -40 - 85 -40 - 85 c dynamic range (note 2) unweighted a-weighted 40 khz bandwidth a-weighted tbd tbd - 99 102 100 - - - tbd tbd - 94 97 97 - - - db db db total harmonic distortion + noise (note 2) 0 db -20 db -60 db thd+n - - - - -91 -79 -39 tbd - - - - - -91 -74 -34 tbd - - db db db interchannel isolation (1 khz) - 102 - - 102 - db parameter symbol min typ max unit combined digital and on-chip analog filter response - single-speed mode (note 4) passband (note 5) to -0.05 db corner to -3 db corner 0 0 - - .4535 .4998 fs fs frequency response 10 hz to 20 khz -.02 - +.035 db stopband .5465 - - fs
cs4360 6 ds517pp1 notes: 4. filter response is guaranteed by design. 5. response is clock dependent and will scale with fs. note that the response plots (figures 9 - 12) have been normalized to fs and can be de-normalized by multiplying the x-axis scale by fs. 6. for single-speed mode, the measurement bandwidth is .5465 fs to 3 fs. for double-speed mode, the measurement bandwidth is .577 fs to 1.4 fs. 7. de-emphasis is available only in single-speed mode. 8. refer to figure 16. stopband attenuation (note 6) 50 - - db group delay tgd - 9/fs - s passband group delay deviation 0 - 20 khz - 0.36/fs - s de-emphasis error (relative to 1 khz) fs = 32 khz control port mode fs = 44.1 khz (note 7) fs = 48 khz fs = 32 khz stand-alone mode fs = 44.1 khz fs = 48 khz - - - - - - - - - - - - +.2/-.1 +.05/-.14 +0/-.22 +1.5/-0 +.05/-.14 +.2/-.4 db db db db db db combined digital and on-chip analog filter response - double-speed mode (note 4) passband (note 5) to -0.1 db corner to -3 db corner 0 0 - - .4621 .4982 fs fs frequency response 10 hz to 20 khz -0.1 - 0 db stopband .577 - - fs stopband attenuation (note 6) 55 - - db group delay tgd - 4/fs - s passband group delay deviation 0 - 20 khz - 0.23/fs - s combined digital and on-chip analog filter response - quad-speed mode (note 4) passband (note 5) to -3 db corner 0 - .25 fs frequency response 10 hz to 20 khz -0.7 - 0 db group delay tgd - 1.5/fs - s parameters symbol min typ max units analog output full scale output voltage 0.60?v a 0.66?v a 0.72?v a vpp quiescent voltage v q - 0.5?v a -vdc quiescent pin external load i q --tbdvdc interchannel gain mismatch - 0.1 - db gain drift - 100 - ppm/c ac-load resistance (note 8) r l 3- -k w load capacitance c l --100pf output impedance z out - 100 - w parameter symbol min typ max unit
cs4360 ds517pp1 7 power and thermal characteristics notes: 9. current consumption is directly proportional to fs. typ and max values are based on highest fs 10. i lc measured with no external loading on pin 12 (sda). 11. power down mode is defined as rst = low with all clock and data lines held static. 12. valid with the recommended capacitor values on filt+ and v cm as shown in figure 4. digital characteristics (for -ks & -kz parts t a = -10 to +70 c; for -bs & -bz parts t a = -40 to +85c; vd = 2.0 v - 5.5 v, vlc = vls = 1.8 v - 5.5 v) parameters symbol min typ max units power supplies power supply current normal operation, all supplies = 5 v (note 9) all supplies = 3 v interface current (note 10) power-down state (all supplies) (note 11) i a i d i a i d i ls i lc i pd - - - - - - - 22 25 21 14 0.002 0.002 0.016 - - - - - - - ma ma ma ma ma ma ma power dissipation (note 9) all supplies = 5 v normal operation power-down (note 11) all supplies = 3 v normal operation power-down (note 11) - - - - 235 0.080 105 0.048 tbd - tbd - mw mw mw mw package thermal resistance soic (-ks & -bs) tssop (-kz & -bz) q ja q jc q ja q jc - - - - tbd tbd tbd tbd - - - - c/watt c/watt c/watt c/watt power supply rejection ratio (1 khz) (note 12) (60 hz) psrr psrr - - 60 40 - - db db parameters symbol min typ max units high-level input voltage serial audio data port control port v ih v ih 70% 70% - - - - vls vlc low-level input voltage serial audio data port control port v il - - - - 20% 20% vls vlc input leakage current i in --10 m a input capacitance - 8 - pf maximum mutec drive current - 3 - ma mutec high-level output voltage v oh va v mutec low-level output voltage v ol 0v
cs4360 8 ds517pp1 absolute maximum ratings (gnd = 0v; all voltages with respect to ground.) warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (gnd = 0v; all voltages with respect to ground.) 13. applies to pins 2, 3, 4, 5, 6, and 7. 14. applies to pins 10, 11, 12, and 13. parameters symbol min max units dc power supply analog power digital power serial audio data interface power control port interface power va vd vls vlc -0.3 -0.3 -0.3 -0.3 6.0 6.0 6.0 6.0 v v v v input current, any pin except supplies i in - 10 ma digital input voltage serial audio data interface control port interface v ind_s v ind_c -0.3 -0.3 vls + 0.4 vlc + 0.4 v v ambient operating temperature (power applied) t a -55 125 c storage temperature t stg -65 150 c parameters symbol min typ max units dc power supply analog power digital power serial audio data interface power (note 13) control port interface power (note 14) va vd vls vlc 2.7 2.0 1.8 1.8 5 5 5 5 5.5 va 5.5 5.5 v v v v
cs4360 ds517pp1 9 switching characteristics (for -ks & -kz parts t a = -10 to +70 c; for -bs & -bz parts t a = -40 to +85c; vls = 1.7 v to 5.5 v; inputs: logic 0 = 0 v, logic 1 = vls cl = 20 pf) notes: 15. this serial clock is available only in control port mode when the mclk divide bit is enabled. parameters symbol min typ max units input sample rate single-speed mode double-speed mode quad-speed mode f s f s f s 4 50 100 - - - 50 100 200 khz khz khz lrck duty cycle 45 50 55 % mclk duty cycle 405060 % sclk frequency - -mclk/2hz sclk frequency note 15 - -mclk/4hz sclk rising to lrck edge delay t slrd 20 - - ns sclk rising to lrck edge setup time t slrs 20 - - ns sdata valid to sclk rising setup time t sdlrs 20 - - ns sclk rising to sdata hold time t sdh 20 - - ns figure 1. serial mode input timing sclkh t slrs t slrd t sdlrs t sdh t sclkl t sdata sclk lrck
cs4360 10 ds517pp1 switching characteristics- control port- two-wire format (note 16) (for -ks & -kz parts t a = -10 to +70 c; for -bs & -bz parts t a = -40 to +85c; vlc = 1.7 v - 5.5 v; inputs: logic 0 = gnd, logic 1 = vlc, c l =30pf) notes: 16. the two-wire format is compatible with the i 2 c protocol. 17. data must be held for sufficient time to bridge the transition time, t fc , of scl. 18. the acknowledge delay is based on mclk and can limit the maximum transaction speed. 19. for single-speed mode, for double-speed mode, for quad-speed mode. parameter symbol min max unit scl clock frequency f scl -100khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 17) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl and sda t rc , t rc -1s fall time scl and sda t fc , t fc -300ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling (note 18) t ack - (note 19) ns 5 256 fs -------------------- - 5 128 fs -------------------- - 5 64 fs ----------------- - t buf t hdst t low t hdd t high t sud stop start sda scl t irs rst t hdst t rc t fc t sust t susp start stop repeated t rd t fd t ack figure 2. control port timing - two-wire format
cs4360 ds517pp1 11 switching characteristics - control port - spi format (for -ks & -kz parts t a = -10 to +70 c; for -bs & -bz parts t a = -40 to +85c; vlc = 1.7 v - 5.5 v; inputs: logic 0 = gnd, logic 1 = vlc, c l =30pf) notes: 20. t spi only needed before first falling edge of cs after rst rising edge. t spi = 0 at all other times. 21. data must be held for sufficient time to bridge the transition time of cclk. 22. for f sck < 1 mhz. parameter symbol min max unit cclk clock frequency f sclk -6mhz rst rising edge to cs falling t srs 500 - ns cclk edge to cs falling (note 20) t spi 500 - ns cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 21) t dh 15 - ns rise time of cclk and cdin (note 22) t r2 -100ns fall time of cclk and cdin (note 22) t f2 -100ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t csh t spi t srs rst figure 3. control port timing - spi format
cs4360 12 ds517pp1 2. typical connection diagram 21 digital audio source vls gnd cs4360 mclk va aout1a 2 3 4 8 0.1 f + 1 f +3 v to +5 v * c/ mode configuration 13 10 12 sdin1 5 dif1/scl/cclk dif0/sda/cdin m1/ad0/cs rst mutec1 optional mute circuit 3.3 f 0.1 f aouta1 c = 4 p fs(r 560) l r l + + 16 15 filt+ vq 11 15 m2 7 6 lrck1 sclk1 sdin3 sdin2 3.3 f 10 k w c 560 w + 28 27 3.3 f 10 k w c 560 w + 26 aoutb1 r l optional mute circuit aouta2 r l 3.3 f 10 k w c 560 w + 25 24 3.3 f 10 k w c 560 w + 23 aoutb2 r l optional mute circuit aouta3 r l 3.3 f 10 k w c 560 w + 18 20 3.3 f 10 k w c 560 w + 19 aoutb3 r l aout1b 0.1 f 3.3 f aout2a mutec2 aout2b aout3a mutec3 aout3b vd 0.1 f + 1 f gnd 9 0.1 f +1.8 v to +5 v * vlc 0.1 f +1.8 v to +5 v * r l +560 +3 v to +5 v * * all supplies can be tied together 22 1 14 sdin4 lrck2 sclk2 4 4 4 figure 4. typical connection diagram
cs4360 ds517pp1 13 3. register quick reference addr function 7 6 5 4 3 2 1 0 1h mode control 1 amute dif2 dif1 dif0 dem1 dem0 fm1 fm0 default 10000000 2h invert signal reserved reserved inv_b3 inv_a3 inv_b2 inv_a2 inv_b1 inv_a1 default 00000000 3h mixing control p1 reserved reserved reserved reserved p1atapi3 p1atapi2 p1atapi1 p1atapi0 default 00001001 4h mixing control p2 reserved reserved reserved reserved p2atapi3 p2atapi2 p2atapi1 p2atapi0 default 00001001 5h mixing control p3 reserved reserved reserved reserved p3atapi3 p3atapi2 p3atapi1 p3atapi0 default 00001001 6h volume control a1 a1_mute a1_vol6 a1_vol5 a1_vol4 a1_vol3 a1_vol2 a1_vol1 a1_vol0 default 00000000 7h volume control b1 b1_mute b1_vol6 b1_vol5 b1_vol4 b1_vol3 b1_vol2 b1_vol1 b1_vol0 default 00000000 8h volume control a2 a2_mute a2_vol6 a2_vol5 a2_vol4 a2_vol3 a2_vol2 a2_vol1 a2_vol0 default 00000000 9h volume control b2 b2_mute b2_vol6 b2_vol5 b2_vol4 b2_vol3 b2_vol2 b2_vol1 b2_vol0 default 00000000 0ah volume control a3 a3_mute a3_vol6 a3_vol5 a3_vol4 a3_vol3 a3_vol2 a3_vol1 a3_vol0 default 00000000 0bh volume control b3 b3_mute b3_vol6 b3_vol5 b3_vol4 b3_vol3 b3_vol2 b3_vol1 b3_vol0 default 00000000 0ch mode control 2 szc1 szc0 cpen pdn popg freeze mclkdiv snglvol default 10 0 11000 0dh revision indicator reserved reserved reserved reserved rev3 rev2 rev1 rev0 default 0000xxxx
cs4360 14 ds517pp1 4. register descriptions note: all registers are read/write in two-wire mode and write only in spi, unless otherwise noted. 4.1 mode control 1 (address 01h) 4.1.1 auto-mute (amute) default = 1 0 - disabled 1 - enabled function: the digital-to-analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. a single sample of non-static data will release the mute. detection and muting is done independently for each channel. the quiescent voltage on the output will be retained and the mute control pin will go active during the mute period. the muting function is affected, similar to volume control changes, by the soft and zero cross bits in the power and muting control register. 4.1.2 digital interface format (dif) default = 000 - format 0 (left justified, up to 24-bit data) function: the required relationship between the left/right clock, serial clock and serial data is defined by the digital interface format and the options are detailed in figures 17-22. 76543210 amute dif2 dif1 dif0 dem1 dem0 fm1 fm0 10000000 dif2 dif1 dif0 description format figure 000 left justified, up to 24-bit data, 017 001 i 2 s, up to 24-bit data 118 010 right justified, 16-bit data 219 011 right justified, 24-bit data 320 100 right justified, 20-bit data 421 101 right justified, 18-bit data 522 110 reserved 111 reserved table 1. digital interface formats - control port mode
cs4360 ds517pp1 15 4.1.3 de-emphasis control (dem) default = 00 00 - disabled 01 - 44.1 khz 10 - 48 khz 11 - 32 khz function: selects the appropriate digital filter to maintain the standard 15 m s/50 m s digital de-emphasis filter re- sponse at 32, 44.1 or 48 khz sample rates. (see figure 23) note: de-emphasis is only available in single-speed mode. 4.1.4 functional mode (fm) default = 00 00 - single-speed mode (2 to 50 khz sample rates) 01 - double-speed mode (50 to 100 khz sample rates) 10 - quad-speed mode (100 to 200 khz sample rates) 11 - reserved function: selects the required range of input sample rates. 4.2 invert signal (address 02h) 4.2.1 invert signal polarity (inv_xx) default = 0 0 - disabled 1 - enabled function: when enabled, these bits invert the signal polarity for each of their respective channels. 4.3 mixing control pair 1 (channels a1 & b1) (address 03h) mixing control pair 2 (channels a2 & b2) (address 04h) mixing control pair 3 (channels a3 & b3) (address 05h) 76543210 reserved reserved inv_b3 inv_a3 inv_b2 inv_a2 inv_b1 inv_a1 00000000 76543210 reserved reserved reserved reserved pxatapi3 pxatapi2 pxatapi1 pxatapi0 00001001
cs4360 16 ds517pp1 4.3.1 atapi channel mixing and muting (atapi) default = 1001 - aoutax = l, aoutbx = r (stereo) function: the cs4360 implements the channel mixing functions of the atapi cd-rom specification. refer to table 2 and figure 24 for additional information. note: all mixing functions occur prior to the digital volume control. mixing only occurs in channel pairs. 4.4 volume control (addresses 06h - 0bh) 4.4.1 mute (mute) default = 0 0 - disabled 1 - enabled function: the digital-to-analog converter output will mute when enabled. the quiescent voltage on the output will be retained. the muting function is effected, similar to attenuation changes, by the soft and zero cross bits. the mutec pin will go active during the mute period if the mute function is enabled for both channels in the pair. atapi3 atapi2 atapi1 atapi0 aoutax aoutbx 0000 mute mute 0001 mute r 0010 mute l 0011 mute [(l+r)/2] 0100 r mute 0101 r r 0110 r l 0111 r [(l+r)/2] 1000 l mute 1001 l r 1010 l l 1011 l [(l+r)/2] 1100[(l+r)/2] mute 1101[(l+r)/2] r 1110[(l+r)/2] l 1111[(l+r)/2] [(l+r)/2] table 2. atapi decode 76543210 xx_mute xx_vol6 xx_vol5 xx_vol4 xx_vol3 xx_vol2 xx_vol1 xx_vol0 00001001
cs4360 ds517pp1 17 4.4.2 volume control (xx_vol) default = 0 function: the digital volume control registers allow independent control of the signal levels in 1 db increments from 0 to -119 db. volume settings are decoded as shown in table 3. the volume changes are im- plemented as dictated by the soft ramp and zero cross bits. all volume settings less than -119 db are equivalent to enabling the mute bit. 4.5 mode control 2 (address 0dh) 4.5.1 soft ramp and zero cross control (szc) default = 10 00 - immediate change 01 - zero cross 10 - soft ramp 11 - soft ramp and zero cross function: immediate change when immediate change is selected all level changes will be implemented immediately in one step. zero cross zero cross enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. the requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independently mon- itored and implemented for each channel. soft ramp soft ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 db steps, from the current level to the new level at a rate of 1 db per 8 left/right clock periods. soft ramp and zero cross soft ramp and zero cross dictates that signal level changes, either by attenuation changes or mut- ing, will occur in 1/8 db steps and will be implemented on successive signal zero crossings. the 1/8 db level changes will occur after timeout periods between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter zero crossings. the zero cross func- tion is independently monitored and implemented for each channel. binary code decimal value volume setting 0001010 0 db 0010100 -20 -20 db 0101000 -40 -40 db 0111100 -60 -60 db 1011010 -90 -90 db table 3. example digital volume settings 76543210 szc1 szc0 cpen pdn popg freeze mclkdiv snglvol 10011000
cs4360 18 ds517pp1 4.5.2 control port enable (cpen) default = 0 0 - disabled 1 - enabled function: the control port will become active and reset to the default settings when this function is enabled. 4.5.3 power down (pdn) default = 1 0 - disabled 1 - enabled function: the entire device will enter a low-power state when this function is enabled, and the contents of the control registers are retained in this mode. the power-down bit defaults to enabled on power-up and must be disabled before normal operation in control port mode can occur. 4.5.4 popguard? transient control (popg) default = 1 0 - disabled 1 - enabled function: the popguard ? transient control allows the quiescent voltage to slowly ramp to and from 0 volts to the quiescent voltage during power-on or power-off when this function is enabled. please see section 6.4 for implementation details. 4.5.5 freeze controls (freeze) default = 0 0 - disabled 1 - enabled function: this function allows modifications to be made to the registers without the changes taking effect until the freeze is disabled. to make multiple changes in the control port registers take effect simulta- neously, enable the freeze bit, make all register changes, then disable the freeze bit. 4.5.6 master clock divide enable (mclkdiv) default = 0 0 - disabled 1 - enabled function: the mclkdiv bit enables a circuit which divides the externally applied mclk signal by 2 prior to all other internal circuitry.
cs4360 ds517pp1 19 4.5.7 single volume control (snglvol) default = 0 0 - disabled 1 - enabled function: the individual channel volume levels are independently controlled by their respective volume control bytes when this function is disabled. the volume on all channels is determined by the a1 channel volume control byte, and the other volume control bytes are ignored when this function is enabled. 4.6 revision register (read only) (address 0dh) 4.6.1 revision indicator (rev) [read only] default = none 0001 - revision a 0010 - revision b 0011 - revision c etc. function: this read-only register indicates the revision level of the device. 76543210 reserved reserved reserved reserved rev3 rev2 rev1 rev0 0000xxxx
cs4360 20 ds517pp1 5. pin description pin name # pin description vls 1 serial audio interface power ( input ) - determines the required signal level for the serial audio inter- face. refer to the recommended operating conditions for appropriate voltages. applies to pins 2-7. sdin1 sdin2 sdin3 2 3 4 serial audio data input ( input ) - input for twos complement serial audio data. sdin1 corresponds to aout1x, sdin2 corresponds to aout2x and sdin3 corresponds to aout3x. sclk 5 serial clock ( input ) - serial clock for the serial audio interface. lrck 6 left / right clock ( input ) - determines which channel, left or right, is currently active on the serial audio data line. the frequency of the left/right clock must be at the audio sample rate, fs. mclk 7 master clock ( input ) - clock source for the delta-sigma modulator and digital filters. table 6 illustrates several standard audio sample rates and the required master clock frequency. vd 8 digital power ( input ) - positive power supply for the digital section. refer to the recommended operat- ing conditions for appropriate voltages. gnd 9 21 ground ( input ) - ground reference. should be connected to analog ground. rst 10 reset ( input ) - the device enters a low power mode and all internal registers are reset to their default settings when low. the control port cannot be accessed when reset is low. vlc 14 control port interface power ( input ) - determines the required signal level for the control port and pro- vides power for bidirectional control port pins. refer to the recommended operating conditions for appropriate voltages. applies to pins 10-13 and 15. filt+ 16 positive voltage reference ( output ) - positive reference voltage for the internal sampling circuits. requires the capacitive decoupling to gnd as shown in the typical connection diagram. serial audio power vls mutec1 mute control 1 serial data input 1 sdin1 aouta1 analog output a1 serial data input 2 sdin2 aoutb1 analog output b1 serial data input 3 sdin3 mutec2 mute control 2 serial clock sclk aouta2 analog output a2 left/right clock lrck aoutb2 analog output b2 master clock mclk va analog power digital power vd gnd ground ground gnd aouta3 analog output a3 reset rst aoutb3 analog output b3 dif1 / scl/ cclk dif1/scl/cclk mutec3 mute control 3 dif0 / sda / cdin dif0/sda/cdin vq quiescent voltage mode1 / ad0 / cs m1/ad0/cs filt+ positive voltage reference control port power vlc m2 mode 2 1 2 3 4 5 6 7 8 9 10 11 12 5 1 2 6 24 23 22 21 20 19 18 17 16 15 14 13 25 26 27 28
cs4360 ds517pp1 21 vq 17 quiescent voltage ( output ) - filter connection for internal quiescent voltage. vq must be capacitively coupled to analog ground, as shown in the typical connection diagram. the nominal voltage level is specified in the analog characteristics and specifications section. vq presents an appreciable source impedance and any current drawn from this pin will alter device performance. however, vq can be used to bias the analog circuitry assuming there is no ac signal component and the dc current is less than the maximum specified in the analog characteristics and specifications section. va 22 analog power ( input ) - positive power supply for the analog section. refer to the recommended oper- ating conditions for appropriate voltages. aouta1 aoutb1 aouta2 aoutb2 aouta3 aoutb3 19 20 23 24 26 27 analog outputs ( output ) - the full scale analog line output level is specified in the analog characteris- tics specifications table. mutec1 mutec2 mutec3 18 25 28 mute control ( output ) - the mute control pin goes high during power-up initialization, reset, muting, power-down or if the master clock to left/right clock frequency ratio is incorrect. this pin is intended to be used as a control for an external mute circuit to prevent the clicks and pops that can occur in any single supply system. the use of an external mute circuit is not mandatory but may be desired for designs requiring the absolute minimum in extraneous clicks and pops. control port definitions scl/cclk 11 serial control port clock ( input ) - serial clock for the serial control port. requires an external pull-up resistor to the logic interface voltage in two-wire mode as shown in the typical connection diagram. sda/cdin 12 serial control data ( input/output ) - sda is a data i/o line in two-wire format and requires an external pull-up resistor to the logic interface voltage, as shown in the typical connection diagram. cdin is the input data line for the control port interface in spi format. ad0/cs 13 address bit 0 (two-wire) / control port chip select (spi) ( input/output ) - ad0 is a chip address pin two-wire format; cs is the chip select signal for spi format. stand-alone definitions dif1 dif0 11 12 digital interface format ( input ) - the required relationship between the left/right clock, serial clock and serial data is defined by the digital interface format selection. refer to table 4. m1 m2 13 15 mode selection ( input ) - determines the operational mode of the device as detailed in table 5. dif1 dif0 description 0 0 left justified, up to 24-bit data 01 i 2 s, up to 24-bit data 1 0 right justified, 16-bit data 1 1 right justified, 24-bit data table 4. digital interface formats - stand alone mode m2 m1 mode 0 0 single-speed without de-emphasis (4 to 50 khz sample rates) 0 1 single-speed with de-emphasis (32 to 48 khz sample rates) 1 0 double-speed (50 to 100 khz sample rates) 1 1 quad-speed (100 to 200 khz sample rates) table 5. mode selection
cs4360 22 ds517pp1 . sample rate (khz) mclk (mhz) 256x 384x 512x 768x 1024x* 32 8.1920 12.2880 16.3840 24.5760 32.7680 44.1 11.2896 16.9344 22.5792 32.7680 45.1584 48 12.2880 18.4320 24.5760 36.8640 49.1520 * requires mclkdiv bit = 1 table 6. single-speed mode common clock frequencies sample rate (khz) mclk (mhz) 128x 192x 256x 384x 512x* 64 8.1920 12.2880 16.3840 24.5760 32.7680 88.2 11.2896 16.9344 22.5792 33.8688 45.1584 96 12.2880 18.4320 24.5760 36.8640 49.1520 * requires mclkdiv bit = 1 table 7. double-speed mode common clock frequencies sample rate (khz) mclk (mhz) 64x 96x 128x 192x 256x* 176.4 11.2896 16.9344 22.5792 33.8688 45.1584 192 12.2880 18.4320 24.5760 36.8640 49.1520 * requires mclkdiv bit = 1 table 8. quad-speed mode common clock frequencies
cs4360 ds517pp1 23 6. applications 6.1 grounding and power supply decoupling as with any high resolution converter, the cs4360 requires careful attention to power supply and grounding arrangements to optimize performance. figure 4 shows the recommended power arrange- ment with va, vd, vls and vlc connected to clean supplies. decoupling capacitors should be lo- cated as close to the device package as possible. if desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be placed on each supply pin. 6.2 oversampling modes the cs4360 operates in one of three oversampling modes based on the input sample rate. mode selec- tion is determined by the fm pins in stand-alone mode or the fm bits in control port mode. single- speed mode supports input sample rates up to 50 khz and uses a 128x oversampling ratio. double- speed mode supports input sample rates up to 100 khz and uses an oversampling ratio of 64x. quad- speed mode supports input sample rates up to 200 khz and uses an oversampling ratio of 32x. 6.3 recommended power-up sequence 1. hold rst low until the power supply, master, and left/right clocks are stable. in this state, the control port is reset to its default settings and vq will remain low. 2. bring rst high. the device will remain in a low power state with vq low and will initiate the stand-alone power-up sequence. the control port will be accessible at this time. if control port oper- ation is desired, write the cpen bit prior to the completion of the stand-alone power-up se- quence, approximately 512 lrck cycles in sin- gle-speed mode (1024 lrck cycles in double- speed mode, and 2048 lrck cycles in quad- speed mode). writing this bit will halt the stand- alone power-up sequence and initialize the control port to its default settings. the desired register set- tings can be loaded while keeping the pdn bit set to 1. 3. if control port mode is selected via the cpen bit, set the pdn bit to 0 which will initiate the pow- er-up sequence, which requires approximately 50 s when the popg bit is set to 0. if the popg bit is set to 1, see section 6.4 for total power-up timing. 6.4 popguard ? transient control the cs4360 uses a novel technique to minimize the effects of output transients during power-up and power-down. this technique, when used with external dc-blocking capacitors in series with the audio outputs, minimizes the audio transients com- monly produced by single-ended single-supply converters. when the device is initially powered-up, the audio outputs, aoutax and aoutbx, are clamped to gnd. following a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent voltage. approximately 10,000 left/right clock cycles later, the outputs reach vq and audio output begins. this gradual voltage ramping allows time for the external dc-blocking capacitor to charge to the quiescent voltage, mini- mizing the power-up transient. to prevent transients at power-down, the device must first enter its power-down state. when this oc- curs, audio output ceases and the internal output buffers are disconnected from aoutax and aoutbx. in their place, a soft-start current sink is substituted which allows the dc-blocking capaci- tors to slowly discharge. once this charge is dissi- pated, the power to the device may be turned off and the system is ready for the next power-on. to prevent an audio transient at the next power-on, it is necessary to ensure that the dc-blocking ca- pacitors have fully discharged before turning off
cs4360 24 ds517pp1 the power or exiting the power-down state. if not, a transient will occur when the audio outputs are ini- tially clamped to gnd. the time that the device must remain in the power-down state is related to the value of the dc-blocking capacitance. for ex- ample, with a 3.3 f capacitor, the minimum pow- er-down time will be approximately 0.4 seconds. use of the mute control function is recommended for designs requiring the absolute minimum in ex- traneous clicks and pops. also, use of the mute control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. see the cdb4360 data sheet for a suggested mute circuit. 7. control port interface the control port is used to load all the internal set- tings. the operation of the control port may be completely asynchronous with the audio sample rate. however, to avoid potential interference prob- lems, the control port pins should remain static if no operation is required. the cs4360 has map auto increment capability, enabled by the incr bit in the map register, which is the msb. if incr is 0, then the map will stay constant for successive writes. if incr is set to 1, then map will auto increment after each byte is written, allowing block reads or writes of succes- sive registers. 7.1 enabling the control port on the cs4360 the control port pins are shared with stand-alone configuration pins. to enable the control port, the user must set the cpen bit. this is done by performing a two-wire or spi write. once the control port is enabled, these pins are ded- icated to control port functionality. to prevent audible artifacts the cpen bit (see sec- tion 4.5.2) should be set prior to the completion of the stand-alone power-up sequence, approximate- ly 512 lrck cycles in single-speed mode (1024 lrck cycles in double-speed mode, and 2048 lrck cycles in quad-speed mode). writing this bit will halt the stand-alone power-up sequence and initialize the control port to its default settings. note, the cpen bit can be set any time after rst goes high; however, setting this bit after the stand- alone power-up sequence has completed can cause audible artifacts. 7.2 format selection the control port has 2 formats: spi and two-wire, with the cs4360 operating as a slave device. if two-wire operation is desired, ad0/cs should be tied to vls or gnd. if the cs4360 ever detects a high to low transition on ad0/cs after power-up and after the control port is activated, spi format will be selected. 7.3 two-wire format in two-wire format, sda is a bidirectional data line. data is clocked into and out of the part by the clock, scl, with a clock to data relationship as shown in figure 5. the receiving device should send an acknowledge (ack) after each byte re- ceived. there is no cs pin. pin ad0 form the par- tial chip address and should be tied to vls or gnd as required. the upper 6 bits of the 7 bit address field must be 001000. note, mclk is required during all two-wire trans- actions. the two-wire format is compatible with the i 2 c protocol. please see reference 2 for further details. 7.3.1 writing in two-wire format to communicate with the cs4360, initiate a start condition of the bus. next, send the chip address. the eighth bit of the address byte is the r/w bit (low for a write). the next byte is the memory address pointer, map, which selects the register to be read or written. the map is then fol- lowed by the data to be written. to write multiple registers, continue providing a clock and data,
cs4360 ds517pp1 25 waiting for the cs4360 to acknowledge between each byte. to end the transaction, send a stop condition. 7.3.2 reading in two-wire format to communicate with the cs4360, initiate a start condition of the bus. next, send the chip address. the eighth bit of the address byte is the r/w bit (high for a read). the contents of the reg- ister pointed to by the map will be output after the chip address. to read multiple registers, continue providing a clock and issue an ack after each byte. to end the transaction, send a stop condi- tion. 7.4 spi format in spi format, cs is the cs4360 chip select signal, cclk is the control port bit clock, cdin is the in- put data line from the microcontroller and the chip address is 0010000. cs , cclk and cdin are all inputs and data is clocked in on the rising edge of cclk. note that the cs4360 is write-only when in spi format. 7.4.1 writing in spi figure 6 shows the operation of the control port in spi format. to write to a register, bring cs low. the first 7 bits on cdin form the chip address and must be 0010000. the eighth bit is a read/write in- dicator (r/w ), which must be low to write. the next 8 bits form the memory address pointer (map), which is set to the address of the register that is to be updated. the next 8 bits are the data which will be placed into register designated by the map. to write multiple registers, keep cs low and continue providing clocks on cclk. end the read transaction by setting cs high. sda scl 001000 addr ad0 r/w start ack data 1-8 ack data 1-8 ack stop note: if operation is a write, this byte contains the memory address pointer, map. note 1 figure 5. control port timing, two-wire format map msb lsb data byte 1 byte n r/w map = memory address pointer address chip cdin cclk cs 0010000 figure 6. control port timing, spi format
cs4360 26 ds517pp1 7.5 memory address pointer (map) 7.5.1 incr (auto map increment enable) default = 0 0 - disabled 1 - enabled 7.5.2 map (memory address pointer) default = 0000 76543210 incr reserved reserved reserved map3 map2 map1 map0 00000000
cs4360 ds517pp1 27 figure 7. base-rate stopband rejection figure 8. base-rate transition band figure 9. base-rate transition band (detail) figure 10. base-rate passband ripple figure 11. high-rate stopband rejection figure 12. high-rate transition band
cs4360 28 ds517pp1 figure 13. high-rate transition band (detail) figure 14. high-rate passband ripple aoutx agnd 3.3 f v out r l c l + figure 15. output test load 100 50 75 25 2.5 51015 safe operating region capacitive load -- c (pf) l resistive load -- r (k w ) l 125 3 20 figure 16. maximum loading
cs4360 ds517pp1 29 lrck sclk left channel right channel sdinx +3 +2 +1 lsb +5 +4 ms b-1-2-3-4-5 +3 +2 +1 ls b +5 +4 m s b-1 -2 -3 -4 figure 17. cs4360 format 0 - left justified up to 24-bit data lrck sclk left channel right channel sdinx +3 +2 +1 ls b +5 +4 m s b-1 -2 -3 -4 -5 +3 +2 +1 ls b +5 +4 msb - 1 -2 -3 -4 figure 18. cs4360 format 1 - i 2 s up to 24-bit data lrck sclk left channel right channel sdinx 6543210 987 15 14 13 12 11 10 6543210 987 15 14 13 12 11 10 32 clocks figure 19. cs4360 format 2 - right justified 16-bit data lrck sclk left channel sdinx 6543210 7 23 22 21 20 19 18 6543210 7 23 22 21 20 19 18 32 clocks 0 right channel figure 20. cs4360 format 3 - right justified 24-bit data
cs4360 30 ds517pp1 lrck sclk left channel right channel sdinx 6543210 987 15 14 13 12 11 10 10 6543210 987 15 14 13 12 11 10 17 16 17 16 32 clocks 19 18 19 18 figure 21. cs4360 format 4 - right justified 20-bit data lrck sclk left channel right channel sdinx 6543210 987 15 14 13 12 11 10 10 6543210 987 15 14 13 12 11 10 17 16 17 16 32 clocks figure 22. cs4360 format 5 - right justified 18-bit data gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 23. de-emphasis curve
cs4360 ds517pp1 31 s a channel volume control aout a aoutb left channel audio data right channel audio data b channel volume control & mute & mute figure 24. atapi block diagram
cs4360 32 ds517pp1 8. parameter definitions total harmonic distortion + noise (thd+n) the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10hz to 20khz), including distortion components. expressed in decibels. dynamic range the ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full scale. this technique ensures that the distortion components are below the noise level and do not affect the measurement. this measurement technique has been accepted by the audio engineering so- ciety, aes17-1991, and the electronic industries association of japan, eiaj cp-307. interchannel isolation a measure of crosstalk between the left and right channels. measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full scale analog output for a full scale digital input. gain drift the change in gain value with temperature. units in ppm/c. 9. references 1) how to achieve optimum performance from delta-sigma a/d & d/a converters by steven harris. paper presented at the 93rd convention of the audio engineering society, october 1992. 2) cdb4360 evaluation board datasheet 3) the i 2 c bus specification: version 2.0 philips semiconductors, december 1998. http://www.semiconductors.philips.com
cs4360 ds517pp1 33 10. package dimensions inches millimeters dim min nom max min nom max a 0.093 0.098 0.104 2.35 2.50 2.65 a1 0.004 0.008 0.012 0.10 0.20 0.30 b 0.013 0.017 0.020 0.33 0.42 0.51 c 0.009 0.011 0.013 0.23 0.28 0.32 d 0.697 0.705 0.713 17.70 17.90 18.10 e 0.291 0.295 0.299 7.40 7.50 7.60 e 0.040 0.050 0.060 1.02 1.27 1.52 h 0.394 0.407 0.419 10.00 10.34 10.65 l 0.016 0.026 0.050 0.40 0.65 1.27 0 4 8 0 4 8 jedec #: ms-013 controlling dimension is millimeters 28l soic (300 mil body) package drawing d h e b a1 a c l seating plane 1 e
cs4360 34 ds517pp1 notes: 1. d and e1 are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension b does not include dambar protrusion/intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of b dimension at maximum material condition. dambar intrusion shall not reduce dimension b by more than 0.07 mm at least material condition. 3. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a----0.47----1.20 a1 0.002 0.004 0.006 0.05 0.10 0.15 a2 0.03150 0.035 0.04 0.80 0.90 1.00 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3 d 0.378 bsc 0.382 bsc 0.386 bsc 9.60 bsc 9.70 bsc 9.80 bsc 1 e 0.248 0.2519 0.256 6.30 6.40 6.50 e1 0.169 0.1732 0.177 4.30 4.40 4.50 1 e -- 0.026 bsc -- -- 0.65 bsc -- l 0.020 0.024 0.029 0.50 0.60 0.75 0 4 8 0 4 8 jedec #: mo-153 controlling dimension is millimeters. 28l tssop (4.4 mm body) package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
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